TRENCH ISOLATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT TO PREVENT STRESS AND DAMAGE OF ACTIVE REGION

摘要

PURPOSE: A trench isolation method of a semiconductor integrated circuit is provided to prevent stress and damage of an active region and to improve reliability of a gate oxide layer by using a double polish stop layer. CONSTITUTION: A mask pattern including a pad oxide pattern, the first polish stop pattern(120), an interlayer dielectric pattern(130) and the second polish stop pattern(140) is formed on a substrate(110). A trench is formed by etching the exposed substrate. The first insulating layer(150) is formed in the resultant structure with the trench. The first insulating layer is polished to expose the second polish stop pattern. The exposed second polish stop pattern is removed. The second insulating layer is formed on the resultant structure. The second and first insulating layer are polished to expose the first polish stop pattern. The exposed first polish stop pattern is then removed.