| 摘要 |
An SQTV processor for converting a video signal received at an interlaced scanning frequency of 50 or 60 Hz, respectively to an interlaced scanning frequency of 100 or 120 Hz and implementing algorithms of noise filtering and of edge definition, including an analog-digital converter (ADC) of analog input signals of luminance and chrominance, at least a field memory (FIELD MEMORY_1) or more preferably two similar field memories where digital blocks of luminance (Y) value and blocks of values of each one of the two chrominance (U, V) components of said converted video signals are stored, one "First-In-First-Out" (LINE MEMORY) register for digital values read from said filed memory containing the pixels of a whole line of each field, a noise filtering block (NOISE REDUCTION), a sampling frequency converter (SRC) of said fields from 50 or 60 Hz to 100 or 120 Hz, means of conversion of the vertical format (VFC), means of edge definition (PE) enhancement and means of digital-to-analog conversion (DAC) of the processed luminance and chrominance (YUV) signals, is further equipped with means for compressing and coding said converted video signals according to an adaptive differential pulse code modulation (ADPCM) scheme of said digital values to be stored in said field memory (FIELD MEMORY_1) and means of ADPCM decoding and decompressing of data read from said field memory (FIELD MEMORY_1). The significative reduction of the total memory requisite produced by the ADPCM pre-compression would make the entire system more readily integratable on a single chip. <IMAGE> |
