发明名称 |
PACKET DATA PROCESSOR |
摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a packet data processor capable of realizing a decoder function with high processing performance for simultaneous processing of a plurality of digital stream data in receiving the data in a processor-based demultiplexing system for processing a plurality of streams. <P>SOLUTION: The packet data processor totally controls a start / end state of each processing unit when applying prescribed demultiplexing processing to a plurality of streams and dynamically switches the processing procedure in accordance with the operating state of each processing unit. Thus, operating a plurality of the processing units in parallel enhances the processing performance. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
申请公布号 |
JP2004289240(A) |
申请公布日期 |
2004.10.14 |
申请号 |
JP20030075667 |
申请日期 |
2003.03.19 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
OKAMOTO AKIRA;GOTO SHOICHI;YAMADA MIKIHIKO |
分类号 |
H04L12/70;H04L12/853;H04L13/08;H04N7/08;H04N7/081;H04N7/173;H04N19/00;H04N19/423;H04N19/436;H04N19/44;H04N19/70 |
主分类号 |
H04L12/70 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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