| 摘要 |
PURPOSE: An apparatus for recovering a clock and a timing of digital packet data is provided to recover the clock from the first data bit by matching the phase of the clock to the data at the initial stage. CONSTITUTION: An apparatus for recovering a clock and a timing of digital packet data includes a first data generation unit, a phase shifter(67), a phase lock loop(64) and a timing recovery unit(66). The first data generation unit detects the first data edge by receiving the edge of the delayed input data and the delayed lock edge. The phase shifter outputs the divided reference clock as an input of the first data edge outputted from the first data generation unit. The phase lock loop outputs the reference clock after the phase difference between the input data and the signal outputted from the phase shifter is detected and filtered. And, the timing recovery unit recovers the timing by removing the jitter of the input data by generating the clock outputted from the phase shifter at the center of the delayed input data.
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