VARIABLE DUTY CYCLE CLOCK GENERATION CIRCUITS AND METHODS AND SYSTEMS USING THE SAME

摘要

A signal generator generates an output signal with a programmable duty cycle and includes a first buffer which generates in response to an input signal an intermediate signal having a selected edge with a voltage slope selected to vary a length of a selected phase of the output signal. A second buffer having a selected input voltage threshold generates the output signal in response to the intermediate signal.