| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit for preventing the occurrence of a delay difference (clock skew) caused by factors that are not detected by simulation, such as manufacturing variations in a minute process and delay calculation errors for preventing errorneous operation in a circuit in a scanning test. SOLUTION: A clock circuit for scanning is separated from a clock circuit for normal operation, lattice wiring S500 is provided at the clock circuit for scanning, a clock signal SCK for scanning is supplied from the lattice wiring S500 to a flip-flop circuit F500 for scanning, thus preventing the occurrence of clock skews affected by delay calculation errors and manufacturing variations in a minute process and errorneous operation in the scanning test and hence solving the problem that the circuit operates erroneously in the scanning test from the skew generated by factors that are not detected by a simulation, such as manufacturing variations and delay calculation errors in a minute process. COPYRIGHT: (C)2005,JPO&NCIPI
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