发明名称
摘要 There is provided an electronic circuit capable of operating in a normal-operating mode and a power-saving mode. The electronic circuit includes a buffer cell having a buffer and an active pull-up unit, and a control circuit configured to invalidate the active pull-up unit and an input signal to the buffer when the electronic circuit has been switched to the power-saving mode.
申请公布号 JP3577053(B2) 申请公布日期 2004.10.13
申请号 JP20020084324 申请日期 2002.03.25
申请人 发明人
分类号 G06K17/00;G06F1/32;H01L21/822;H01L27/04;H03K19/0175 主分类号 G06K17/00
代理机构 代理人
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