发明名称
摘要 <p>PROBLEM TO BE SOLVED: To provide a multilayer interconnecting board wherein the difference between the deformation behavior of semiconductor part's chip constitution part and that of a wiring board is relaxed. SOLUTION: A multilayer interconnection board 6 is provided where, with a land 10 formed, a semiconductor part 1 comprising a plurality of electrodes 5 formed in matrix provided with a chip constitution part A, where a semiconductor chip 2 is sealed and a sealing resin constitution part B positioned around the chip constitution part A is mounted. Here, a depletion area 11 formed when a part of layer is removed is formed on the non-mounting surface of a chip projection area C which is a position corresponding to the chip constituting part A.</p>
申请公布号 JP3575310(B2) 申请公布日期 2004.10.13
申请号 JP19990018382 申请日期 1999.01.27
申请人 发明人
分类号 H05K1/18;H01L23/12;H05K3/46;(IPC1-7):H01L23/12 主分类号 H05K1/18
代理机构 代理人
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