发明名称 |
Liner for semiconductor memories and manufacturing method therefor |
摘要 |
A manufacturing method for an integrated circuit memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer. First and second bitlines are implanted and a wordline layer is deposited. A hard mask layer is deposited over the wordline layer. A photoresist is deposited over the wordline layer and used to form a hard mask. The photoresist is removed. The wordline layer is processed using the hard mask to form a wordline and the hard mask is removed. A reduced hydrogen, ultra-violet block data retention liner covers the wordline and the charge-trapping dielectric layer. The reduced hydrogen levels reduce the charge loss compared to prior art. The surface of the liner is processed to block UV light before completing the integrated circuit.
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申请公布号 |
US6803265(B1) |
申请公布日期 |
2004.10.12 |
申请号 |
US20020109234 |
申请日期 |
2002.03.27 |
申请人 |
FASL LLC |
发明人 |
NGO MINH VAN;HALLIYAL ARVIND;KAMAL TAZRIEN;SHIRAIWA HIDEHIKO;SUGINO RINJI;HOPPER DAWN M.;GAO PEI-YUAN |
分类号 |
H01L21/8246;H01L23/26;H01L27/115;(IPC1-7):H01L21/337 |
主分类号 |
H01L21/8246 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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