发明名称 Checkerboard buffer using memory bank alternation
摘要 Methods and apparatus for storing and retrieving data in parallel but in different orders. In one implementation, data for pixels for one frame is stored according to a checkerboard pattern, alternately between two memory devices, forming a checkerboard buffer. While data is being stored, data for pixels from another frame is retrieved from another two memory devices. The banks of devices alternate between storing and retrieving with each frame. In one implementation, a checkerboard buffer includes: a data source, providing data in a first order; a data destination, receiving data in a second order; at least four memory devices, each memory device having a plurality of memory locations, where data is stored in parallel to at least two memory devices and retrieved in parallel from at least two memory devices; a first data switch connected to the data source and each of the memory devices, where the first data switch controls which data is stored to which memory device; and a second data switch connected to the data destination and each of the memory devices, where the second data switch controls providing data to the data destination according to the second order.
申请公布号 US6803917(B2) 申请公布日期 2004.10.12
申请号 US20010908301 申请日期 2001.07.17
申请人 SONY CORPORATION;SONY ELECTRONICS INC. 发明人 CHAMPION MARK;DOCKTER BRIAN
分类号 G06T1/60;G09G3/00;G09G3/34;G09G5/39;G09G5/391;G09G5/393;G09G5/395;G09G5/399;G11C7/10;H04N5/14;H04N5/44;H04N5/46;H04N5/74;H04N7/01;(IPC1-7):G09G5/399 主分类号 G06T1/60
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