CIRCUIT FOR MULTIPLEXING OUTPUT OF DOUBLE DATA RATE SYNCHRONOUS MEMORY DEVICE(DDR SRAM) AND ITS METHOD

摘要

PURPOSE: A circuit for multiplexing an output of a double data rate synchronous memory device and its method are provided to reduce a chip area and to enable a high frequency operation. CONSTITUTION: According to the circuit for multiplexing an output of a double data rate synchronous memory device, the N number of first latches(L01-L04) prefetch n bit data transmitted through a data path from a memory cell array simultaneously. The N number of first switches(S01-S04) transfer n bit data prefetched by the first latches to N number of nodes, in response to a CAS latency information signal. The second switches(S21-S24) transfer data on the nodes in sequence, in response to N number of signals generated in sequence by being synchronized to a clock signal. The second latches(L11-L14) store data transferred through the second switches. And the third switches(S31-S34) transfer data stored in the second latch to an input port of an output driver of the memory device at a rising edge and a falling edge of a delay signal of the clock signal.