发明名称 Technique for reducing memory latency during a memory request
摘要 A technique for reducing the latency associated with a memory read request. A bypass path is provided to direct the address of a corresponding request to a memory controller. The memory controller initiates a speculative read request to the corresponding address location. In the meantime, the original request is decoded and directed to the targeted area of the system. If the request is a read request, the memory controller will receive the request, and after comparing the request address to the address received via the bypass path, the memory controller will cancel the request since the speculative read has already been issued. If the request is directed elsewhere or is not a read request, the speculative read request is cancelled.
申请公布号 US6804750(B2) 申请公布日期 2004.10.12
申请号 US20020054255 申请日期 2002.01.22
申请人 MICRON TECHNOLOGY, INC. 发明人 LABERGE PAUL A.
分类号 G06F13/16;(IPC1-7):G06F12/00 主分类号 G06F13/16
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