| 摘要 |
PURPOSE: A semiconductor memory device is provided to reduce a bit line loading generated in a NAND flash memory and to improve a read speed and a verify speed. CONSTITUTION: According to the semiconductor memory device including a memory cell array(110) comprising a number of cell strings and a top/bottom page buffer(120,130) which is arranged on a top/bottom part of the memory cell array and constitutes the cell string through a number of bit lines. In the device, a number of top/bottom bit lines are isolated electrically up and down to reduce the loading of the bit line during a read/program verify operation. A top selection circuit(140) allocates one of the adjacent top bit lines to the top page buffer according to an address signal. And a bottom selection circuit(150) allocates one of the adjacent bottom bit lines to the bottom page buffer according to the address signal.
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