| 摘要 |
PROBLEM TO BE SOLVED: To match gate delay specified with a first logical input and gate delay specified with a second logical input. SOLUTION: A load resistor and first and second differential transistor couples 1, 2 are longitudinally piled up in the direction of a voltage, third and fourth differential transistor couples 3, 4 are longitudinally piled up on the load resistor, and the first logical input is inputted to the first and fourth differential transistor couples. The second logical input is then inputted to the second and fourth differential transistor couples, and an AND output is obtained from the load resistor. COPYRIGHT: (C)2005,JPO&NCIPI
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