发明名称 Low noise divider module for use in a phase locked loop and other applications
摘要 A low noise divider module includes a divider chain and a retiming module. The divider chain includes a plurality of cascaded dividers and a plurality of load logic gates. The plurality of cascaded dividers are operably coupled to divide an input oscillation by a divider value, which is programmable, to produce a divided output oscillation based on the load signals provided by the logic gates. The retiming module includes a duty cycle module and a jitter reduction module. The duty cycle module is coupled to produce a duty cycle controlled output oscillation based on a representation of the divided output oscillation produced by the divider chain in accordance with a duty cycle setting signal. The jitter reduction module is operably coupled to produce a low jitter output oscillation from the duty cycle controlled output oscillation based on the input oscillation and the duty cycle setting signal.
申请公布号 US2004196940(A1) 申请公布日期 2004.10.07
申请号 US20030406178 申请日期 2003.04.03
申请人 CHIEN HUNG-MING (ED) 发明人 CHIEN HUNG-MING (ED)
分类号 H03K21/10;H03K23/66;H03L7/183;(IPC1-7):H03D3/24 主分类号 H03K21/10
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