| 摘要 |
In a dual loop PLL having a frequency comparison loop and a phase comparison loop, when an input control circuit 30 of an up/down counter 8 receives an UP signal from a frequency comparator 7, the input control circuit 30 outputs a positive value of a ½ of a previous addition/subtraction result value. When the input control circuit 30 receives a DOWN signal from the frequency comparator 7, the input control circuit 30 outputs a negative value of a ½ of the previous addition/subtraction result value. A register 33 stores a count value. The adder 31 adds the output of the input control circuit 30 to the output of the register 33. Thus, the up/down counter 8 increments or decrements by a ½ value of the previous addition/subtraction result value, and the dual loop PLL performs a frequency comparison based on a dichotomizing search method. Therefore, even when the output frequency is high, the frequency comparison is efficiently performed, and the lock up time is reduced.
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