发明名称 |
Single-chip microcomputer |
摘要 |
A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.
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申请公布号 |
US2004199716(A1) |
申请公布日期 |
2004.10.07 |
申请号 |
US20040824219 |
申请日期 |
2004.04.13 |
申请人 |
KAWASAKI SHUMPEI;AKAO YASUSHI;NOGUCHI KOUKI;HASEGAWA ATSUSHI;OHSUGA HIROSHI;KURAKAZU KEIICHI;MATSUBARA KIYOSHI;HAYAKAWA AKIO;ITO YOSHITAKA |
发明人 |
KAWASAKI SHUMPEI;AKAO YASUSHI;NOGUCHI KOUKI;HASEGAWA ATSUSHI;OHSUGA HIROSHI;KURAKAZU KEIICHI;MATSUBARA KIYOSHI;HAYAKAWA AKIO;ITO YOSHITAKA |
分类号 |
G06F13/28;G06F9/30;G06F9/302;G06F9/38;G06F12/00;G06F12/08;G06F13/36;G06F13/40;G06F15/78;H04L12/28;(IPC1-7):G06F15/00 |
主分类号 |
G06F13/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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