| 摘要 |
PROBLEM TO BE SOLVED: To lay out low power consumption bus wiring of a semiconductor integrated circuit. SOLUTION: A layout method of bus wiring of a semiconductor integrated circuit includes a step of laying out bus wiring in each functional block of a semiconductor integrated circuit, a first step of delay simulation for analyzing data transfer delays on all bit wires in all buses by a bus operation test, a second step of computing a delay time from a reference clock at each signal variation timing of all bit wires according to the delay simulation, and computing an average value of delay time of each bit wire according to each computed delay time, and a third step of computing differences in the average delay time value between adjacent bit wires, and rearranging the array of the bit wires so as to maximize the total of the average value differences between all bit wires. COPYRIGHT: (C)2005,JPO&NCIPI
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