| 摘要 |
PROBLEM TO BE SOLVED: To provide a remainder calculation apparatus whose processing performance per circuit scale is optimized to prevent excess delay from being caused due to the calculation of t. SOLUTION: The remainder calculation apparatus 14 performs pipeline processing by making a plurality of processing units 31 including a product-sum circuit 32 successively and continuously perform processing and repeatedly performs the pipeline processing. For example, in processing N(1)t(2), since N(1)t(1) and x(0)y(2) can not follow, N(1)t(1)+x(0)y(2) is calculated in advance by t calculating section 40 other than the pipeline processing to obtain t(2) in advance. By using the t(2), N(0)t(2) is processed. When the number of the processing units 31 is smaller than the number of words of modulus N, a plurality of words whose operands are in sequence are equally processed by each processing unit 31. COPYRIGHT: (C)2005,JPO&NCIPI
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