| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory device which can perform a normal operation even when entry is performed erroneously for a test mode and external applying voltage for an internal circuit is low. SOLUTION: A mode is shifted to an internal power source applying mode in accordance with a test mode signal TE being made a H level due to malfunction. Supply of reference voltage Vref from a reference voltage generating circuit 11 is stopped to a node A on peripheral power source wiring CPL, while P channel MOS transistors P1, P2 are turned on and applying voltage is supplied to an external pin PIN. At the time, a potential of the node A becomes 2×Vthp (Vthp: threshold voltage of P channel MOS transistor) or more surely. When the number of P channel MOS transistors is set so that this lowest potential is at a voltage level at which peripheral circuits 21 can be operated, the normal operation can be performed in the peripheral circuits 21 even when the external applying voltage is low. COPYRIGHT: (C)2005,JPO&NCIPI
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