发明名称 Semiconductor memory device
摘要 Positive/negative bit lines are arranged on a second-layer interconnection the VDD power supply interconnection is arranged between the positive/negative bit lines, the word line is arranged on a third-layer interconnection, and the VSS power supply interconnection is arranged on a fourth-layer interconnection. Alternatively, the word line is arranged on the second-layer interconnection, the positive/negative bit lines are arranged on the third-layer interconnection, the VDD power supply interconnection is arranged between the positive/negative bit lines, and the VSS power supply interconnection is arranged on the fourth-layer interconnection. Alternatively, the VDD power supply interconnection is arranged on the second-layer interconnection, the positive/negative bit lines are arranged on the third-layer interconnection, the word line is arranged on the fourth-layer interconnection, and the VSS power supply interconnection is arranged on the fifth-layer interconnection.
申请公布号 US2004196705(A1) 申请公布日期 2004.10.07
申请号 US20040808402 申请日期 2004.03.25
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 ISHIKURA SATOSHI;SATOMI KATSUJI
分类号 G11C11/41;G11C7/00;H01L21/8244;H01L27/11;(IPC1-7):G11C7/00 主分类号 G11C11/41
代理机构 代理人
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