| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory test circuit capable of testing a memory having a data width larger than that of a CPU data bus without increasing the number of test cycles. SOLUTION: For example, when a memory 1 is tested by a marching algorithm, the write data WDT of n-bit all "0" is outputted from a CPU 2. A uppermost significant bit is expanded by a bit expansion part 11, and given as the data of m (>n) bit all "0" to the data input terminal of the memory 1. On the other hand, the m-bit data read from the memory 1 are divided into n bit units by a selector 12, and given as read data RDT to the CPU 2. COPYRIGHT: (C)2005,JPO&NCIPI
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