发明名称 Delay-compensated fractional-N frequency synthesizer
摘要 A Phase-Locked Loop is provided that includes a main loop, a calibration loop, and Control Logic. The main loop comprises, coupled in series, a Phase Frequency Detector, a Main Charge Pump, a Main Loop Filter, a Voltage Controlled Oscillator and a Frequency Divider. The calibration loop is coupled to the Phase Frequency Detector and comprises a Calibration Charge Pump and a Calibration Loop Filter. The Control Logic controls the Frequency Divider and receives a control input signal. A Reference Frequency Signal is coupled to the Phase Frequency Detector and the Control Logic, and a calibration signal is coupled to the calibration loop. Additionally, the main loop further comprises a delay generator controlled by the Control Logic and arranged to receive correction signals from the calibration loop and to send an output signal to the Phase Frequency Detector.
申请公布号 US2004196108(A1) 申请公布日期 2004.10.07
申请号 US20030737532 申请日期 2003.12.16
申请人 STMICROELECTRONICS BELGIUM N.V. 发明人 CRANINCKX JAN FRANS LUCIEN
分类号 H03L7/081;H03L7/089;H03L7/197;(IPC1-7):H03L7/00 主分类号 H03L7/081
代理机构 代理人
主权项
地址