| 摘要 |
PURPOSE: An apparatus for generating clock signals in a digital TV is provided to generate the clock signals suitable for environment having various display formats. CONSTITUTION: The first PLL(Phase Locked Loop) block(11) performs the PLL process of the first system clock, and outputs the first output clock. The first multiplexing output unit(14) selectively outputs the first and second system clocks by the first clock selection signal. The second PLL block(12) performs the PLL process of the system clock outputted from the first multiplexing output unit using frame rate information, and outputs the second output clock for VCR. The second multiplexing output unit(15) selectively outputs the first output clock and the first system clock by the second clock selection signal. The third PLL block(13) performs the PLL process of the clock signal outputted from the second multiplexing output unit at constant times by a constant time selection signal, and outputs the third output clock. |
