| 摘要 |
Semiconductor devices such as DRAM cells include adjacent conductive patterns 55, for example bit lines or gate stacks, each comprising a conductive line 50 and a capping layer 60 on a semiconductor substrate. In order to reduce lateral erosion of sidewall spacers during etching to form contact holes, a first spacer layer 70 is deposited between adjacent conductor lines, then a second spacer layer 80 is deposited conformally over the conductor stacks and over first spacer layer. An interlayer insulating layer 90 is formed on the conformal spacer layer, then the first spacer layer is etched using the second spacer layer as a mask, to form a single-layer spacer 85 which comprises two different dielectric materials, on the sidewalls of the conductive lines, concurrently with forming a contact hole 100. |
