| 摘要 |
PURPOSE: A row decoder is provided which has a high processing speed and low power consumption, by dividing a load capacitance at a drain port of a NMOS transistor for address decoding and improving a precharge speed and by discharging the load capacitance at the drain port of the NMOS transistor and improving a decoding speed. CONSTITUTION: A precharge unit(MP20) is connected between a power supply voltage and the first node, and precharges the first node by a clock signal. A decoder is connected between the second node and a ground, and decodes an address signal. A divider(MN38) is connected between the first node and the second node, and divides load capacitance(Cd) of the address decoder by the clock signal. A discharge unit(MN3A) is connected with the address decoder in parallel between the second node and the ground, and discharges the load capacitance of the address decoder in a precharge state by an inverted clock signal. And an output unit outputs an address decoding signal by inverting a potential of the first node.
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