发明名称 |
Process for enhancement of voltage endurance and reduction of parasitic capacitance for a trench power MOSFET |
摘要 |
A process for a trench power MOSFET comprises forming a trench on a semiconductor substrate and an oxide and nitride in the trench, etching the oxide and nitride to remain a part of them at the bottom of the trench, and subsequent procedure for the other structure of the trench power MOSFET. Due to the thick insulator formed at the bottom of the trench, the trench power MOSFET is improved by increased voltage endurance and reduced parasitic capacitance, and thereby the cell density is increased.
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申请公布号 |
US6800509(B1) |
申请公布日期 |
2004.10.05 |
申请号 |
US20030601651 |
申请日期 |
2003.06.24 |
申请人 |
ANPEC ELECTRONICS CORPORATION |
发明人 |
LIN MING-JANG;LIAW CHORNG-WEI;LIN WEI-JYE |
分类号 |
H01L21/28;H01L21/336;H01L29/417;H01L29/423;H01L29/51;H01L29/78;(IPC1-7):H01L21/332;H01L21/320;H01L21/476 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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