| 摘要 |
A level-shifting circuit. The first PMOS transistor includes a first gate, a first drain, and a first source coupled to a first voltage VDD. The second PMOS transistor includes a second gate coupled to the first drain, a second drain coupled to the first gate, and a second source coupled to the first voltage VDD. The first inverse logic gate includes an output terminal and is coupled to the first drain. The second inverse logic gate includes an inverse output terminal and coupled to the second drain. The first NMOS transistor includes a third gate coupled to the first voltage VDD, a third drain coupled to the first drain, and a third source coupled to an inverse input terminal. The second NMOS transistor includes a fourth gate coupled to the first voltage VDD, a fourth drain coupled to the second drain, and a fourth source coupled to an input terminal.
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