| 摘要 |
An efficient graphics pipeline with a pixel cache and data pre-fetching. By combining the use of a pixel cache in the graphics pipeline and the pre-fetching of data into the pixel cache, the graphics pipeline of the present invention is able to take best advantage of the high bandwidth of the memory system while effectively masking the latency of the memory system. More particularly, advantageous reuse of pixel data is enabled by caching, which when combined with pre-fetching masks the memory latency and delivers high throughput. As such, the present invention provides a novel and superior graphics pipeline over the prior art in terms of more efficient data access and much greater throughput. In one embodiment, the present invention is practiced within a computer system having a processor for issuing commands; a memory sub-system for storing information including graphics data; and a graphics sub-system for processing the graphics data according to the commands from the processor. The graphics sub-system comprises a rasterizer for traversing graphics primitives of the graphics data to generate pixel coordinates for pixels corresponding to the graphics primitives; a graphics pipeline for processing the graphics data of the pixels; and a pixel cache for caching the pixel data. In this embodiment, he graphics sub-system masks the inherent latency of the memory sub-system by pre-fetching the graphics data and storing the graphics data within the pixel cache.
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