发明名称 |
Semiconductor device capable of avoiding latchup breakdown resulting from negative variation of floating offset voltage |
摘要 |
A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region (28), a p<+>-type impurity region (33) is formed between an NMOS (14) and a PMOS (15) and in contact with a p-type well (29). An electrode (41) resides on the p<+>-type impurity region (33) and the electrode (41) is connected to a high-voltage-side floating offset voltage (VS). The p<+>-type impurity region (33) has a higher impurity concentration than the p-type well (29) and is shallower than the p-type well (29). Between the p<+>-type impurity region (33) and the PMOS (15), an n<+>-type impurity region (32) is formed in the upper surface of the n-type impurity region (28). An electrode (40) resides on the n<+>-type impurity region (32) and the electrode (40) is connected to a high-voltage-side floating supply absolute voltage (VB).
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申请公布号 |
US2004189353(A1) |
申请公布日期 |
2004.09.30 |
申请号 |
US20040762340 |
申请日期 |
2004.01.23 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
HATADE KAZUNARI;AKIYAMA HAJIME;SHIMIZU KAZUHIRO |
分类号 |
H01L27/04;H01L21/761;H01L21/822;H01L21/8238;H01L23/58;H01L27/092;H01L27/108;H01L29/76;H01L29/94;H01L31/119;H03B1/00;(IPC1-7):H03B1/00 |
主分类号 |
H01L27/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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