发明名称 |
CMOS DEVICE INTEGRATION FOR LOW EXTERNAL RESISTANCE |
摘要 |
The present invention relates to a Complementary Metal Oxide Semiconductor (CMOS) device having a lower external resistance and a method for manufacturing the CMOS device. The inventive MOSFET is produced by forming first silicide regions in a substrate as well as atop surface of a gate region and forming second silicide regions where second silicide thickness is greater than the first silicide thickness. The inventive method produces a low resistance first silicide in close proximity to the channel region of the device, where the incorporation of the first silicide decreases the external resistance of the device while the incorporation of the second silicide produces low sheet resistance interconnects.
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申请公布号 |
US2004188765(A1) |
申请公布日期 |
2004.09.30 |
申请号 |
US20030249295 |
申请日期 |
2003.03.28 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
NARASIMHA SHREESH;O'NEIL PATRICIA A. |
分类号 |
H01L21/336;(IPC1-7):H01L29/76;H01L29/94;H01L31/062;H01L31/113;H01L31/119 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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