| 摘要 |
A mixed signal integrated circuit including an embedded ROM array is manufactured using a two polysilicon process, with small critical dimensions. A first layer of polysilicon covered with a dielectric, adapted for formation of transistor gates and capacitor bottom electrodes, is formed in a non-array portion of the substrate. A second layer of polysilicon, adapted for formation of word lines in the array portion of the substrate, and capacitor top electrodes, is formed over the dielectric layer. The second layer of polysilicon is patterned to define word lines in the array portion and the capacitor top electrodes. Next, the array portion and the capacitor top electrodes are protected, and the first layer of polysilicon is patterned, to define transistor gates and the capacitor bottom electrodes. Salicide processing is applied to the non-array portion of the integrated circuit.
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