发明名称 VERTICAL SIDEWALL PROFILE SPACER LAYER AND METHOD FOR FABRICATION THEREOF
摘要 A method for forming a spacer layer adjoining a substantially vertical first sidewall of a topographic feature within a microelectronic product employs an anisotropic etching of a reentrant spacer material layer formed upon the topographic feature. The spacer layer is formed at least in part with a substantially vertical second sidewall laterally separated from the substantially vertical first sidewall. The method is useful for forming spacer layers within field effect transistor devices.
申请公布号 US2004188779(A1) 申请公布日期 2004.09.30
申请号 US20030401714 申请日期 2003.03.27
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. 发明人 LIU SHIH-CHIANG;LO CHI-HSIN;TSAI CHIA-SHIANG
分类号 H01L21/311;H01L21/316;H01L21/336;(IPC1-7):H01L29/76;H01L31/062;H01L21/338 主分类号 H01L21/311
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