发明名称 SIGNAL PROCESSOR, PREFETCH INSTRUCTION METHOD, AND PREFETCH INSTRUCTION PROGRAM
摘要 <P>PROBLEM TO BE SOLVED: To automatically prefetch data in a cache as seamless data without performing an address calculation or determination processing related to loop processing which has been essentially carried out in software in the software. <P>SOLUTION: This method comprises a processor 1; a cache memory 11 arranged therein; a processing execution part 2 contained in the processor 1 and comprising a command decoding part/issuing part 5 a register file 6, a prefetch execution control part 7, an external memory control part 8, a cache memory control part 9 and a data processing part 12; and an external memory 10 arranged out of the processor 1. When loop data are read from the external memory 10 to the cache memory 11, the loop data are continuously read by automatically returning to a starting point at the termination. <P>COPYRIGHT: (C)2004,JPO&NCIPI
申请公布号 JP2004272851(A) 申请公布日期 2004.09.30
申请号 JP20030066443 申请日期 2003.03.12
申请人 TOSHIBA CORP 发明人 AZUMA TETSUHIKO
分类号 G06F12/08;G06F9/30;G06F9/345;G06F9/38;G06F9/44;G06F9/45;G10L13/00 主分类号 G06F12/08
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