发明名称 |
Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line |
摘要 |
A self aligned method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The drain region is formed underneath the trench, and the channel region includes a first portion that extends vertically along a sidewall of the trench and a second portion that extends horizontally along the substrate surface. An electrically conductive floating gate is formed over and insulated from a portion of the channel region. A raised source line of conductive material is disposed over the source region, and laterally adjacent to and insulated from the floating gate. An electrically conductive control gate is formed having a first portion disposed in the trench and a second portion formed over but insulated from the floating gate.
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申请公布号 |
US2004191990(A1) |
申请公布日期 |
2004.09.30 |
申请号 |
US20040818590 |
申请日期 |
2004.04.05 |
申请人 |
KIANIAN SOHRAB;WANG CHIH HSIN |
发明人 |
KIANIAN SOHRAB;WANG CHIH HSIN |
分类号 |
G11C16/04;H01L21/8247;H01L27/115;H01L29/788;(IPC1-7):G11C11/34 |
主分类号 |
G11C16/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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