USE OF BYPASSING IN A PIPELINED INSTRUCTION PROCESSOR
摘要
An instruction processing device has a of pipe-line stage with a functional unit for executing a command from an instruction. A first register unit is coupled to the functional unit for storing a result of execution of the command when the command has reached a first one of the pipeline stages, and for supplying bypass operand data to the functional unit. A register file is coupled to the functional unit for storing the result when the command has reached a second one of the pipeline stages, downstream from the first one of the pipeline stages, and for supplying operand data to the functional unit. A disable circuit is coupled to selectively disable storing of the results in the register file under control of the instructions.
申请公布号
WO2004084065(A2)
申请公布日期
2004.09.30
申请号
WO2004IB50270
申请日期
2004.03.17
申请人
KONINKLIJKE PHILIPS ELECTRONICS N.V.;SRINIVASAN, BALAKRISHNAN;SETHURAMAN, RAMANATHAN;ALBA PINTO, CARLOS, A.
发明人
SRINIVASAN, BALAKRISHNAN;SETHURAMAN, RAMANATHAN;ALBA PINTO, CARLOS, A.