发明名称 LOGICAL VERIFICATION DEVICE AND METHOD, RECORDING MEDIUM AND PROGRAM
摘要 PROBLEM TO BE SOLVED: To provide a logical verification device and method for shortening logical verification time by avoiding to repeat the same processing several times by using the same simulator. SOLUTION: An instruction level simulator 1 executes first instruction level simulation concerning a pre-processing instruction group in a test program, and an instruction level simulation result storing part 3 stores the execution result. A logic simulator 4 and an instruction level simulator 1 performs a simulation to execute an instruction group to be tested by using the execution result stored in the instruction level simulation result storing part 3. COPYRIGHT: (C)2004,JPO&NCIPI
申请公布号 JP2004272524(A) 申请公布日期 2004.09.30
申请号 JP20030061306 申请日期 2003.03.07
申请人 NEC CORP 发明人 SHIRATORI YUKO
分类号 G06F17/50;G06F9/455;(IPC1-7):G06F17/50 主分类号 G06F17/50
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