发明名称 PACKAGE STRUCTURE WITH INCREASED CAPACITANCE AND METHOD
摘要 A package with increased capacitance comprises a core and a plurality of buildup layers. The core has an inner dielectric portion and the core outer conductive layer. The buildup layers are disposed over the core and have offset ablated regions reducing the thickness of the buildup layers in the ablated regions. Conductive material is plated on the buildup layers including within the ablated regions. The reduced thickness and increased plate area due to the ablated regions increases the capacitance between adjacent buildup layers. Processors and processing systems may take advantage of the increased capacitance in the package to draw more current and operate at higher data rates.
申请公布号 US2004188825(A1) 申请公布日期 2004.09.30
申请号 US20030401379 申请日期 2003.03.27
申请人 INTEL CORPORATION 发明人 SURVAKUMAR MAHADEVAN
分类号 H01L23/498;H01L23/50;H05K1/16;H05K3/00;H05K3/46;(IPC1-7):H01L23/053 主分类号 H01L23/498
代理机构 代理人
主权项
地址
您可能感兴趣的专利