LAYOUT OF ESD PROTECTION DEVICE TO OPTIMIZE CAPACITANCE AND RESISTANCE VALUE

摘要

PURPOSE: A layout of an ESD(electrostatic discharge) protection device is provided to optimize capacitance and a resistance value necessary for gate coupling in which a resistor is connected between a gate and a power supply terminal or a ground terminal by connecting a capacitor between the gate and an input pad and by extending the poly line of the gate in embodying the gate coupling. CONSTITUTION: Each gate of an NMOSFET(n-channel metal-oxide-semiconductor field-effect-transistor)/PMOSFET is widely extended by a poly material so as to separately form the lower electrode(24) of a coupling capacitor. A gap between the drains of the NMOSFET/PMOSFET is widely extended by a metal material to cover the lower electrode by a width of an active region so that the upper electrode(22) of the coupling capacitor is connected to the drain. A coupling resistor is connected to the gate of the NMOSFET/PMOSFET and the power supply terminal/the ground terminal by a poly line of a winding type.