发明名称 |
Word-line voltage generator |
摘要 |
A programmable memory circuit includes a memory array having a plurality of floating gate memory cells disposed in a first and second row and at least a first and second column and a reference circuit for providing a word line voltage to the memory array for programming selected memory cells from a selected one of the first and second rows. The word line voltage is dependent at least in part upon a bit line reference voltage and upon a threshold voltage of a reference floating gate cell associated with the selected one of the first and second rows.
|
申请公布号 |
US2004190340(A1) |
申请公布日期 |
2004.09.30 |
申请号 |
US20030397574 |
申请日期 |
2003.03.26 |
申请人 |
CHIH YUE-DER;KUO CHENG-HSIUNG |
发明人 |
CHIH YUE-DER;KUO CHENG-HSIUNG |
分类号 |
G11C5/14;G11C8/08;G11C11/34;G11C16/06;G11C16/08;G11C16/12;(IPC1-7):G11C11/34 |
主分类号 |
G11C5/14 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|