发明名称 |
Flash memory with improved erasability and its circuitry |
摘要 |
A negative-voltage bias circuit is provided which comprises: a capacitor (550) having first and second terminals (550B, 550A) ; a first p-channel MIS field-effect transistor (551) whose drain is connected to a negative-voltage output terminal (554) and whose gate and source are connected to the first terminal (550B) of the capacitor (550); and a second p-channel MIS field-effect transistor (552) whose drain is connected to the source of the first p-channel MIS field effect transistor (551), whose gate is connected to the negative-voltage output terminal (554), and whose source is provided with a negative voltage (VBB). The first p-channel MIS field-effect transistor (551) is a depletion-type p-channel MIS field-effect transistor. In operation of the circuit, application to the second terminal (550A) of a series of clock pulses (CLK) causes a potential of the negative-voltage output terminal (554) to tend towards the negative voltage (VBB). <IMAGE> |
申请公布号 |
EP1168362(A3) |
申请公布日期 |
2004.09.29 |
申请号 |
EP20010121238 |
申请日期 |
1992.12.09 |
申请人 |
FUJITSU LIMITED |
发明人 |
AKAOGI, TAKAO;KAWASHIMA, HIROMI;TAKEGUCHI, TETSUJI;HAGIWARA, RYOJI;KASA, YASUSHI;ITANO, KIYOSHI;KAWAMURA, SHOUICHI;OGAWA, YASUSHIGE |
分类号 |
G05F3/20;G11C5/14;G11C16/04;G11C16/06;G11C16/08;G11C16/16;G11C16/30;G11C29/00;H03K3/356;H03K19/0185;H03K19/21;(IPC1-7):G11C16/06 |
主分类号 |
G05F3/20 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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