CMOS-compatible read only memory and method for fabricating the same

摘要

A CMOS-compatible read only memory (ROM) (10, 11) includes a first single-poly PMOS transistor (101) that is serially electrically connected to a second single-poly PMOS transistor (102) for recording digital data "1" or digital data "0". The first and second single-poly PMOS transistors (101, 102) are both formed on an N-well (100) of a P-type substrate. The first single-poly PMOS transistor (101) includes a select gate (301) electrically connected to a word line (30), a first P<+> source doping region (201) electrically connected to a source line, and a first P<+> drain doping region. The second single-poly PMOS transistor (102) includes a floating gate (302), a second P<+> source doping region electrically connected to the first P<+> drain doping region, and a second P<+> drain doping region (203) electrically connected to a bit line. The second P<+> source doping region and the second P<+> drain doping region define a floating gate channel region (401) under the floating gate. A fast FPLD-to-ROM conversion method is also disclosed. After the final software code is fixed and the addresses where the memory units to be coded are determined, the FPLD are transformed into a ROM by either changing the layout of a photo mask that is used to define polysilicon gates to cancel the pre-selected floating gates according to the fixed software code, or by ion implanting the pre-selected floating gate channel regions underneath those floating gates (302) where the memory units are to be coded. <IMAGE>