| 摘要 |
An output buffer circuit disclosed herein includes a buffer supplied with an input signal and outputting an output signal from an output terminal; a driving assistant buffer including a first MISFET provided at one of a first position and a second position, the first position being between the output terminal and a first power supply and the second position being between the output terminal and a second power supply; a first logic circuit configured to perform a logic operation based on a first logical threshold using the output signal to output a first logic signal; a second logic circuit configured to perform the same logic operation as the first logic circuit based on a second logical threshold using the output signal to output a second logic signal; and a third logic circuit outputting a control signal to control the first MISFET and including second and third MISFETs connected in series, the first logic signal being inputted to a gate of the second MISFET and the second logic signal being inputted to a gate of the third MISFET.
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