Storage array such as a SRAM with reduced power requirements

摘要

A CMOS storage array such as a static random access memory (SRAM) and a sense amplifier. The SRAM may be in partially depleted (PD) silicon on insulator (SOI) and may include fully depleted (FD) FETs. A power line supply select at each row selectively increases cell supply voltage to a full supply voltage when the row is selected. A word line decoder selects a row of cells that are provided the supply voltage and cells in remaining rows are provided a reduced supply voltage. Leakage is substantially lower in said remaining rows than in said selected row. The sense amplifier may include cross coupled FD NFETs sensing stored data. A read/write-select in each bit path selectively blocks cell writes when cell contents are not being changed. Power is not expended unnecessarily writing to cells.