| 摘要 |
A reference voltage circuit is provided in which a difference of voltages applied to reference voltage circuits is reduced so that a difference of respective output voltages is made small. Depletion type MOS transistors (3, 6) are respectively connected in series with the drains of depletion type MOS transistors (1, 4) in two ED type reference voltage circuits. The gate of one of the series-connected depletion type MOS transistors (3, 6) is connected with the source of the other MOS transistor and the gate of the other MOS transistor is connected with the source of the one MOS transistor. Thus, a difference of voltages applied to the respective ED type reference voltage circuits is reduced so that a difference of respective output voltages is made small. |
