| 摘要 |
PROBLEM TO BE SOLVED: To easily specify an error position in layout verification of a semiconductor integrated circuit having a hierarchical structure. SOLUTION: The method for verifying the layout of the semiconductor integrated circuit includes a step of extracting power source wiring and ground wiring of an upper stage layer based on layout data built in each hierarchical cell (S200), a step of assigning a layer different from the layer of the other wiring layer to the extracted power source wiring and the ground wiring (S300), a step of forming a chip layout on the hierarchical cell based on the layout data (S400), and a step of outputting information for specifying a shorting position (S700) when the short circuit of the power source wiring and the ground wiring is sensed based on the layer of the chip layout (YES in step S500). COPYRIGHT: (C)2004,JPO&NCIPI
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