| 摘要 |
PROBLEM TO BE SOLVED: To prevent smoothness and a frequency characteristic of original data from being lost even when arithmetic processing with a decreased number of bits is applied to a received digital signal. SOLUTION: A signal processing apparatus 10 sequentially receives digital signals Xn each having a consecutive relation, applies a prescribed arithmetic operation to each digital signal, and outputs its arithmetic result, and is provided with: a higher-order part extract means (a higher-order bit register 13 and a higher-order bit adder 15) that applies a prescribed arithmetic operation to the received digital signal Xn, rounds off the obtained arithmetic result, and extracts only a higher-order part required for an output; a difference calculation means (a lower-order bit register 14 and a lower-order bit adder 16) that calculates a difference between the obtained arithmetic result and the higher-order part extracted by the higher-order part extract means; and a feedback means ( from a fractional processing register 18 to an input to an input adder 12) that adds a value calculated by the difference calculation means to a succeeding digital signal. COPYRIGHT: (C)2004,JPO&NCIPI
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