发明名称 DISCHARGE BREAKDOWN PREVENTION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a circuit capable of preventing the breakdown of internal data due to electrostatic discharge while suppressing an influence on normal operation. SOLUTION: The circuit is a discharge breakdown prevention circuit in an LSI (large scale integrated circuit) chip where when first and second control signals (/CE, /OE) simultaneously become a first level, a first internal operation (reading) is started, and when the first control signal and a third control signal (/CE, /WE) simultaneously become the first level, a second internal operation (writing) is started. The circuit includes a detection circuit (50) for detecting that the second and third control signals (/OE, /WE) simultaneously become the first level, and a propagation control circuit (52) for prohibiting the propagation of the first control signal (/CE) to the internal circuit in response to an output (S50) of the detection circuit. Hereby, when there is detected a state where the second and third control signals impossible to be generated in normal operation control simultaneously become the first level, the propagation of the first control signal for controlling the starting of the internal operation to the internal circuit is prohibited, so that it is possible to prevent the propagation of a glitch to the internal circuit which might cause erroneous operation accompanying the discharge of static electricity. COPYRIGHT: (C)2004,JPO&NCIPI
申请公布号 JP2004265473(A) 申请公布日期 2004.09.24
申请号 JP20030052430 申请日期 2003.02.28
申请人 FUJITSU LTD 发明人 YAMAZAKI HIROKAZU
分类号 G11C11/417;(IPC1-7):G11C11/417 主分类号 G11C11/417
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