| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce the number of signal lines which are necessary for transferring serial image signals and the number of input and output pins and the like. <P>SOLUTION: An interface device 26 is composed of an output circuit 27A which transfers a serial image signal and a receiving circuit 27B which receives a transfer signal SD. A pixel clock generating circuit of the output circuit 27A generates a pixel clock signal PCLK. A bit clock generating circuit 30 generates a bit clock signal BCLK of a frequency N<SB>1</SB>/N<SB>2</SB>times (N<SB>1</SB>and N<SB>2</SB>are positive integers, and N<SB>1</SB>is an integral multiple of N<SB>2</SB>) as high as the frequency of the pixel clock signal PCLK and supplies it to a dynamicizer circuit 32. The dynamicizer circuit 32 converts the N<SB>1</SB>(=8)-bit wide serial image signal PD into the N<SB>2</SB>(=2)-bit wide transfer signal SD. A staticizer circuit 40 of the receiving circuit 27B converts the transfer signal SD into the N<SB>1</SB>-bit wide serial image signal PD by using the bit clock signal BCLK and the pixel clock signal PCLK. <P>COPYRIGHT: (C)2004,JPO&NCIPI |
