| 摘要 |
PURPOSE: A hardware structure for embodying an error diffusion algorithm is provided to reduce a time required for operation performance to process an image signal and reduce a hardware size. CONSTITUTION: An adding block(61) adds error values of diffused peripheral pixels and an input value. An error value convergence unit(62) clips an output value of the adding block, perform the SHR(Shift Right) of the clipped value, and outputs a threshold designation operation previous value(A). A threshold designation operation unit(63) designates and operates a threshold value, and lastly outputs a threshold designation operation next value(B). A current pixel error value calculating unit(64) bit-concatenates the designation operation previous value and the threshold designation operation next value, and calculates a current pixel error value. An error value weight diffusion unit(65) multiplies the current pixel error value by a weight value, diffuses the multiplied value, and performs an SHL(Shift Left) operation and a subtract operation. An error value weight output unit(66) outputs the error values of the diffused peripheral pixels.
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